U.S. Pat. No. 6,709,562 B1 discloses a method for producing a sub-micron interconnection structure on an integrated circuit chip, which comprises forming an insulation material on a substrate, forming trenches in said insulation by a photolithography technique; forming a conductive layer as an electroplating base on said insulation material; electroplating a seamless conductor in an electroplating bath containing copper ions and additives; and removing the electroplated conductor layer outside the trenches by polishing. The disclosure of said patent is incorporated herein by reference.
U.S. Pat. No. 5,916,642 discloses a method of encapsulating a material in a carbon nanotube comprising generating a vapor of the material to be encapsulated, generating a hydrogen arc discharge that discharges encapsulating material and the products discharged from the hydrogen arc discharge proximate a surface to encapsulate the material in a carbon nanotube. However, this method is not applicable on a substrate with a large surface area.